MMU 8722 (Memory Management Unit) reference

MMU register set:
    7 6 5 4 3 2 1 0
$D500 (R/W)CR Bank select High RAM/ROM Mid RAM/ROM Lo R/R Chargen
$D501 (R/W)PCRA  
$D502 (R/W)PCRB  
$D503 (R/W)PCRC  
$D504 (R/W)PCRD  
$D505 (R/W)MCR 40/80 ² C64 Mode EXROM ² GAME ² FSDIR unused ¹ Z80/8502
$D506 (R/W)RCR Video Bank unused Shared Hi Shared Lo Shared RAM Size
$D507 (R/W)P0L Zero Page A15 - A8
$D508 (R/W)P0H unused ¹ Zero Page A19 - A16
$D509 (R/W)P1L Stack Page A15 - A8
$D50A (R/W)P1H unused ¹ Stack Page A19 - A16
$D50B (R)VR Bank version (2 = 128K) MMU version (0)
$FF00 (R/W)CR Bank select High RAM/ROM Mid RAM/ROM Lo R/R Chargen
$FF01 (R/W)LCRA  
$FF02 (R/W)LCRB  
$FF03 (R/W)LCRC  
$FF04 (R/W)LCRD  

¹ - Unused bits read back 1
² - Read only


High RAM/ROM ($C000-$FFFF):
%00 System ROM (Kernal, Editor)
%01 Internal Function ROM
%10 External Function ROM
%11 RAM


Mid RAM/ROM ($8000-$BFFF):
%00 System ROM (Basic Hi)
%01 Internal Function ROM
%10 External Function ROM
%11 RAM


Low RAM/ROM ($4000-$7FFF):
0 System ROM (Basic Lo)
1 RAM


Chargen ($D000-$DFFF):
0 I/O
1 ROM/RAM


Shared RAM Size:
%00 1K
%01 4K
%10 8K
%11 16K


40/80:
0 40/80 key locked
1 40/80 key released


FSDIR (fast serial disk control bit):
0 fast serial output
1 fast serial input


Z80/8502:
0 Z80 active
1 8502 active


The registers at $FF00 to $FF04 are always mapped in, independent from the ROM/RAM/IO settings.

Changing the memory mapping of the C128 usually is done by changing the configuration register at $FF00 ($D500), but it can also be done via the pre-configuration registers (PCRs) and the load configuration registers (LCRs). To do that you store your settings of the configuration register (CR) to the PCRs at $D501-$D504. If you write anything to the LCRs at $FF01-$FF04, the value in the PCRs is automatically transferred to the CR. This way you can switch between multiple CR settings without overwriting a CPU register.


© 2017 Graham

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